1. Field of the Invention
The present invention relates to display devices and, in particular, a current-driven, self-luminous display device such as an electro-luminescence element. More particularly, the present invention relates to a self-luminous display device having a smaller number of pattern lines for a fixed voltage, in which a source voltage of a transistor driving a light emitting element is set to a fixed voltage to correct variations in emission luminance due to variations in a threshold voltage value of the transistor, and the fixed voltage is set by a signal level of a drive pulse signal on-off controlling a transistor supplying the first transistor with power.
2. Description of the Related Art
A variety of techniques have been introduced in display devices employing an organic electroluminescence (EL) element as discussed in U.S. Pat. No. 5,684,365 and Japanese Unexamined Patent Application Publication No. 8-234683.
FIG. 15 is a block diagram illustrating an active-matrix display device 1 employing an organic EL element of related art. A pixel section 2 in the display device 1 includes a matrix of pixels (PX) 3. A scanning line (SCN) runs in a substantially horizontal direction along each row of pixels 3 arranged in a matrix configuration, and signal lines SIG run substantially in perpendicular to the scanning lines SCN along each column of the pixels.
As shown in FIG. 16, each pixel 3 includes an organic EL element 8 as a current-driven self-luminous element and a driver circuit for each pixel 3 driving the organic EL element 8 (hereinafter referred to as a pixel circuit).
In the pixel circuit, one terminal of a signal level maintaining capacitor C1 is maintained at a constant voltage level, and the other terminal of the signal level maintaining capacitor C1 is connected to a signal line SIG via a transistor TR1 that is turned on and off in response to a write signal WS. In the pixel circuit, the transistor TR1 is turned on at a rising edge of the write signal WS, the other terminal of the signal level maintaining capacitor C1 is set to a signal level of the signal line SIG, and the signal level of the signal line SIG is sample-held to the other terminal of the signal level maintaining capacitor C1 at a timing the transistor TR1 is transitioned from an on state to an off state.
In the pixel circuit, the other terminal of the signal level maintaining capacitor C1 is connected to a gate of a P-channel transistor TR2 having a source connected to a power source Vcc. The drain of the transistor TR2 is connected to an anode of the organic EL element 8. The pixel circuit is set so that the transistor TR2 always operates in a saturation state. As a result, the transistor TR2 forms a constant current circuit operating at a drain-source current Ids represented by the following equation (1):Ids=½×μ×W/L×Cox(Vgs−Vth)2  (1)where Vgs is a gate-source voltage of the transistor TR2 and μ is a mobility, W is a channel width, L is a channel length, Cox is a gate capacitance, and Vth is a threshold voltage of the transistor TR2. In the pixel circuit, the organic EL element 8 is driven by the drive current Ids responsive to the signal level of the signal line SIG sample-held by the signal level maintaining capacitor C1.
The display device 1 generates the write signal WS, as a timing signal for commanding writing to each pixel 3, by successively transferring predetermined sampling pulses with a write-scan circuit (WSCN) in a vertical driver circuit 4. A horizontal selector (HSEL) 5A in a horizontal driver circuit 5 generates a timing signal by successively transferring predetermined sampling pulses and sets each signal line SIG to the signal level of an input signal Si with respect to the timing signal. The display device 1 sets the terminal voltage of the signal level maintaining capacitor C1 in each pixel section 2 in response to the input signal S1 on a dot-by-dot basis or on a line-by-line basis and then displays an image responsive to the input signal S1.
As shown in FIG. 17, current-voltage characteristics of the organic EL element 8 age with time in a direction that current flowing becomes difficult. In FIG. 17, label L1 represents initial characteristics and label L2 represents aged characteristics. In the pixel circuit of FIG. 16, the P-channel transistor TR2 drives the organic EL element 8. In such a case, the transistor TR2 drives the organic EL element 8 in response to the gate-source voltage Vgs set at the signal level of the signal line SIG. Luminance change in each pixel due to aged current-voltage characteristics is prevented.
If the pixel circuit, the horizontal driver circuit 5 and the vertical driver circuit 4 are all constructed of N-channel transistors, these circuits may be fabricated together on an insulating substrate such as a glass substrate in an amorphous silicon process. The display device is thus easily manufactured.
In the comparison of FIG. 18 with FIG. 16, each pixel 13 is fabricated of an N-channel transistor TR2, and a display device 11 is manufactured of pixel sections 12, each including the pixel 13. With the source of the transistor TR2 connected to the organic EL element 8, the gate-source voltage Vgs of the transistor TR2 changes in response to a change in the current-voltage characteristics of FIG. 17. In this case, the current flowing through the organic EL element 8 becomes gradually smaller with time and luminance of each pixel 13 becomes gradually lower. As shown in FIG. 18, emission luminance also varies from pixel to pixel in accordance with variations in the characteristics of the transistor TR2. The variations in the emission luminance disturbs uniformity of a display screen. A user may notice resulting non-uniformity on the display screen.
A circuit arrangement of FIG. 19 has been proposed to control a drop in the emission luminance due to aging of the organic EL element and variations in the emission luminance due to variations in the characteristics of the transistor.
In a display device 21 of FIG. 19, a pixel section 22 includes a matrix of pixels 23. In the pixel 23, one terminal of the signal level maintaining capacitor C1 is connected to an anode of the organic EL element 8 and the other terminal of the signal level maintaining capacitor C1 is connected to the signal line SIG via the transistor TR1 that is turned on and off in response to the write signal WS. In the pixel 23, the voltage of the other terminal of the signal level maintaining capacitor C1 is set to the signal level of the signal line SIG in response to the write signal WS.
In the pixel 23, the two terminals of the signal level maintaining capacitor C1 are respectively connected to the source and the gate of the transistor TR2. The drain of the transistor TR2 is connected to the power source Vcc via the transistor TR3 that is turned on and off in response to a drive pulse signal DS. The organic EL element 8 in the pixel 23 is driven by the transistor TR2. The transistor TR2 forms a source follower with the gate thereof set at the signal level of the signal line SIG. Here, Vcat represents a cathode voltage of the organic EL element 8. The drive pulse signal DS is a timing signal controlling an emission period of each pixel 23. The drive scan circuit (DSCN) 24B generates the drive pulse signal DS by successively transferring predetermined sampling pulses.
The two terminals of the signal level maintaining capacitor C1 are connected to predetermined fixed voltages Vofs and Vss via transistors TR4 and TR5 that are turned on and off in response to control signals AZ1 and AZ2, respectively. The control signal generators 24C and 24D in a vertical driver circuit 24 generate control signals AZ1 and AZ2 as timing signals by successively transferring predetermined sampling pulses.
FIG. 20 is a timing diagram of one pixel 23 in the display device 21. FIG. 20 also shows reference symbols of transistors that are turned on and off in response to corresponding signals. As shown in FIG. 21, during an emission period T1 for causing the organic EL element 8 to emit light, transistors TR1, TR4 and TR5 in the pixel 23 are turned off in response to falling edges of the write signal WS and the control signals AZ1 and AZ2 (waveform diagrams (A)-(C) in FIG. 20). The transistors TR3 is turned on in response to a rising edge of the drive pulse signal DS (waveform diagram (D) of FIG. 20).
The transistor TR2 and the signal level maintaining capacitor C1 in the pixel 23 form a constant current circuit responding to the gate-source voltage Vgs, namely, a voltage difference between the two terminals of the signal level maintaining capacitor C1. The organic EL element 8 emits light in response to the drive current Ids determined by the gate-source voltage Vgs. Luminance drop of the organic EL element 8 due to aging is thus controlled. The drive current Ids is expressed by equation (1) discussed with reference to FIG. 16. In the discussion that follows, each transistor is shown in each figure as a reference symbol of a corresponding switch as appropriate.
The transistors TR4 and TR5 in the pixel 23 remains turned on during a period T2 in succession to the end of an emission period T1 as shown in FIG. 22. The two terminals of the signal level maintaining capacitor C1 in the pixel 23 are set to predetermined fixed voltages Vofs and Vss (waveform diagrams (E) and (F) of FIG. 20). The drive current Ids corresponding to the gate-source voltage Vgs, namely, a voltage difference Vofs-Vss of the predetermined fixed voltages Vofs and Vss flows from the transistor TR2 to the transistor TR5. The fixed voltages Vofs and Vss are set within the period T2 so that the organic EL element 8 may not emit light as a result of an increase of the voltage difference between the two terminals of the organic EL element 8 in excess of the voltage threshold value Tthe1 of the organic EL element 8 and so that the transistor TR2 operates in the saturation region thereof.
Throughout a predetermined period T3, the transistor TR5 in the pixel 23 remains turned off as shown in FIG. 23. As represented by a broken line in FIG. 23, the drain-source current Ids of the transistor TR2 in the pixel 23 causes the voltage at the terminal of the signal level maintaining capacitor C1 connected to the transistor TR5 to rise.
FIG. 24 illustrates an equivalent circuit of the organic EL element 8 as a parallel circuit of a diode and a capacitor having a capacitance of Ce1. The drain-source current Ids of the transistor TR2 causes a source voltage Vs of the transistor TR2 to rise gradually during the period T3 as shown in FIG. 25. In the pixel 23, the voltage difference between the two terminals of the signal level maintaining capacitor C1 is set to a threshold voltage value Vth of the transistor TR2 and the voltage at the terminal of the signal level maintaining capacitor C1 connected to the transistor TR5 is set to a voltage Vofs-Vth resulting from subtracting the threshold voltage value Vth of the transistor TR2 from the fixed voltage Vofs. In this condition, an anode voltage Ve1 of the organic EL element 8 is represented by Ve1=Vofs−Vth. The fixed voltage Vofs is set to result in condition Ve1≦Vcat+Vthe1 in the display device 21 so that the organic EL element 8 may not emit light during the period T3.
The transistors TR3 and TR4 in the pixel 23 are turned off one after another within a period T4 as shown in FIG. 26. With the transistor TR3 turned off prior to turning off the transistor TR4, variations in a gate voltage Vg of the transistor TR2 are controlled. The transistor TR1 in the pixel 23 is then turned off, causing the voltage at the terminal of the signal level maintaining capacitor C1 connected to the transistor TR5 to a signal level Vsig of the signal line SIG when the voltage at the terminal of the signal level maintaining capacitor C1 connected to the transistor TR5 is at the voltage Vofs−Vth.
The gate-source voltage Vgs of the transistor TR2 is expressed in equation (2):Vgs=Ce1/(Ce1+C1+C2)×(Vsig−Vofs)+Vth  (2)where C2 represents a gate-source capacitance of the transistor TR2. If a parasitic capacitance Ce1 of the organic EL element 8 is larger than each of a capacitance of the signal level maintaining capacitor C1 and a gate-source capacitance C2 of the transistor TR2, the gate-source voltage Vgs of the transistor TR2 is set to a voltage (Vsig+Vth) at a practically high accuracy level.
The gate-source voltage Vgs of the transistor TR2 in the pixel 23 is thus set to the voltage (Vsig+Vth) that is obtained by adding the threshold voltage value Vth to the signal level Vsig of the signal line SIG. The display device 21 thus controls variations in the emission luminance that is caused by variations, as one of the characteristics of the transistor TR2, in the threshold voltage value Vth.
The transistor TR3 is turned on with the transistor TR1 remaining on within a constant period T5 as shown in FIG. 27. The transistor TR2 in the pixel 23 allows the drain-source current Ids to flow out in response to the gate-source voltage Vgs corresponding to the voltage difference across the two terminals of the signal level maintaining capacitor C1. If the source voltage Vs of the transistor TR2 is lower than the sum of the threshold voltage value Vthe1 and the cathode voltage Vcat of the organic EL element 8 and a current flowing into the organic EL element 8 is small, the source voltage Vs of the transistor TR2 gradually rises from a voltage Vs0 in response to the drain-source current Ids of the transistor TR2 as shown in FIG. 38. The voltage Vs0 is calculated from the following equation (3):Vs0=Vofs−Vth+(C1+C2)/(Ce1+C1+C2)×(Vsig−Vofs)  (3)
The rising rate of the source voltage Vs depends on a mobility μ of the transistor TR2. The reference symbols Vs1 and Vs2 represent respectively the source voltages for high and low mobilities μ. The higher the mobility, the higher the rising rate of the source voltage Vs results.
The transistor TR3 in the pixel 23 is turned on with transistor TR1 left on during the constant period T5. Variations in the emission luminance due to variations in the mobility, as one of the characteristics of the transistor TR2, are thus controlled.
With the transistor TR1 turned off as shown in FIG. 21, the organic EL element 8 is driven by the gate-source voltage Vgs set with the voltage threshold value Vth and the mobility μ corrected. With the transistor TR1 off, the source voltage Vs of the transistor TR2 rises to a voltage level that permits the drain-source current Ids of the transistor TR2 flows into the organic EL element 8. The organic EL element 8 thus emits light and the gate voltage Vg of the transistor TR2 also rises.
The circuit arrangement of FIG. 19 reduces a drop in the emission luminance of the organic EL element 8 as a result of aging and controls variations in the emission luminance due to variations in the characteristics of the transistor TR2.
For each pixel 23, the circuit arrangement of FIG. 19 includes a single signal line SIG, four scanning lines of the control signals AZ1 and AZ2, the drive pulse signal DS and the write signal WS and four wiring pattern lines of pixel voltages Vcc, Vofs, Vss and Vcat. Even if scanning lines are commonly shared by red color, blue color and green color and the cathode voltage Vcat is arranged separately, 3×3 wiring pattern lines are required for a set of a red pixel, a blue pixel and a green pixel.
The display device employing the N-channel transistors has the problem of too many wiring pattern lines for fixed voltages. Many wiring pattern lines for the fixed voltage present difficulty efficiently arranging pixels at a high density. It becomes difficult to manufacture high-definition display devices at a high yield.